1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device with contacts formed in self-alignment manner.
2. Description of Related Art
A semiconductor integrated circuit formed on a semiconductor substrate such as a silicon substrate has been developed to be integrated with higher density. In a static random access memory (SRAM) as one of such integrated circuits, the memory capacity is increased from 4 Mbits to 16 Mbits and from 16 Mbits to a further more bits. In addition to the high density integration, high speed operation and low power consumption are required in the SRAM. In a large scale integrated circuit inclusive of not only the SRAM but also the dynamic random access memory (DRAM), many semiconductor elements need to be formed on a chip. The chip size needs to be reduced as small as possible from the viewpoints of the device cost and the product yield.
In the SRAM which has a complicated memory cell structure and needs fine processing, the chip size depends on the size of a memory cell. Therefore, in order to reduce the chip size, it is necessary to reduce the size of the memory cell. Specifically, it is very important to reduce the margin of a contact hole for a semiconductor circuit pattern in the memory cell, because many patterns such as diffusion layer patterns of transistors, gate electrode patterns, power supply line patterns and element isolation insulating film patterns, are formed in the memory cell and there are many contacts between these patterns. For this reason, it is desirable to form the contact holes in the semiconductor circuit pattern in self-alignment manner.
FIG. 1 is a plane pattern diagram of a conventional SRAM memory cell. This memory cell of a CMOS type is composed of 6 MOS transistors. FIGS. 2A to 2F are cross sectional views cut along a line A-A' of the SRAM memory cell shown in FIG. 1 in the manufacturing processes.
Referring to FIG. 1, active regions 102-1, 102-2, 103-1 and 103-2 surrounded by an element isolation insulating film 101-1 are formed on a P-type semiconductor (silicon) substrate or P-type well. Then, a gate electrode 104-1 for a drive MOS transistor and a gate electrode 104-2 for a load MOS transistor are provided and a word line 105-1 functioning as a gate electrode for a transfer MOS transistor is provided. N-type diffusion layers are formed as source/drain regions of the drive MOS transistor and load transfer MOS transistor by performing ion implantation of arsenic atoms as impurity into regions of the silicon active regions 102-1 and 102-2 where the above gate electrodes are not formed. Boron atoms as impurity are introduced by ion implantation into regions of the silicon active regions 103-1 and 103-2 where the gate electrodes are not formed, such that P-type diffusion layers are formed as the source/drain regions of the load MOS transistor. Thereafter, an interlayer insulating film is formed to cover the entire surface. Contact holes 106-1 and 106-2 for connecting to the ground potential are formed to pass through the interlayer insulating film. Source regions of the drive MOS transistors are connected to the ground potential wiring patterns (not shown) via the contact holes 106-1 and 106-2. Contact holes 108-1 and 108-2 for connecting to power supply potential pattern are formed and the power is supplied to the load MOS transistors via the contact holes 108-1 and 108-2. Subsequently, contact holes 107-1, 107-2, 109-1 and 109-2 are formed and contacts 107-1 and 109-1 are connected by a pattern (not shown). As a result, the drain region of the drive MOS transistor, the load/drive gate electrode 104-2 and the drain region of the load MOS transistor are electrically connected. Similarly, a pattern (not shown) is formed between the connection contact holes 107-2 and 109-2. As a result, the drain region of the load MOS transistor, the load/drive gate electrode 104-1 and the drain region of the drive MOS transistor are electrically connected. Further, contact holes 110-1 and 110-2 for bit lines are formed.
In this manner, at least 10 contact holes are required in the conventional CMOS type static memory cell as shown in FIG. 1. The connection contact hole 107-1 is formed over the drain region of the drive MOS transistor formed in the silicon active region 102-1 and the gate electrode 104-2. Similarly, the connection contact hole 109-2 is formed over the drain region of the load MOS transistor formed in the silicon active region 103-2 and the gate electrode 104-1.
Next, a method of forming the contact holes will be described with reference to FIGS. 2A to 2F. Referring to FIG. 2A, an element isolation insulating film 202 is selectively formed on the surface of a silicon substrate 201. Subsequently, a gate insulating film 203 is formed for the load MOS transistors. Then, polyside film 204 is deposited and the first resist mask 205 is formed. Next, the polyside film 204 is etched by a dry etching method using the first resist mask 205. Thus, load/drive gate electrodes 206 and 206a are formed as shown in FIG. 2B.
Next, a silicon oxide film is deposited on the entire surface and then anisotropic etching is executed wholly by a dry etching method. As a result, side wall insulating films 207 are formed on the side wall of the load/driving gate electrodes 206 and 206a, as shown in FIG. 2C. Subsequently, P-type diffusion layers 208 are formed through ion implantation of boron and heat treatment. The P-type diffusion layers 208 function as the source/drain regions of the load MOS transistor.
Next, as shown in FIG. 2D, an interlayer insulating film 209 is formed. Then, the second resist mask 210 is formed. The interlayer insulating film 209 is etched by a dry etching method using the second resist mask 210 to form contact holes. A contact hole overhanging the load/drive gate electrode 206a and the diffusion layers 208 is also formed. This contact hole corresponds to the connection contact hole 109-2 in FIG. 1.
Next, as shown in FIG. 2E, a metal thin film 211 is formed and the third resist mask 212 is formed. The metal thin film 211 is etched by a dry etching method using the third resist mask 212. As a result, connection pattern 108-2, 109-2, 109-1 and 108-1 are formed as shown in FIG. 2F.
In the conventional method of forming the contacts, as described above, it is difficult to form the side wall insulating films on the side walls of the gate electrode of the MOS transistor and to form the contact holes on the source/drain regions of gate electrode of the MOS transistor. For this reason, in a case of high density SRAM in which many contact holes are to be formed, it is difficult to reduce the size of a memory cell.